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標題: N5 Datasheet 2-CH Universal RX(up to 8M 15P) [打印本頁]

作者: SGX 時間: 2025-5-28 01:22
標題: N5 Datasheet 2-CH Universal RX(up to 8M 15P)
RX的規格書N5 N5-Datasheet-release-v00-20200303.pdf

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N5_Datasheet_release_v00_20200303.pdf (1.22 MB, 售價: 5 E幣)
高達8M 15P的信號，暗示N5在解析度和帶寬上有較高的性能。 3. **通用性**: 作為一款通用接收器，N5可能設計有廣泛的兼容性，能夠適應多種不同的應用場景。 4. **質量保證**: 產品設計注重高質量信號接收，可能具備低噪聲、高信噪比等特性，以確保數據的準確傳輸。 5. **安全性警告**: 明確指出產品不適用于生命支持應用，這是為了遵守行業規定和安全標準。文檔還提醒用戶，盡管提供了信息，但Nextchip不對文檔內容導致的任何損害負責，而且提供的信息“AS IS”，即不提供任何明示或暗示的保證。此外，Nextchip不承擔因使用這些信息而產生的間接損害的責任。 Nextchip公司的聯系信息也在文檔中給出，包括網址、電子郵件地址和電話號碼，方便用戶獲取更多產品支持和服務。總體來說，N5是一款面向特定領域的高性能接收器，適用于需要高質量信號處理的系統。其設計考慮了多種使用環境，但明確排除了醫療領域的應用。用戶在使用N5時，應遵循文檔的指導，確保正確理解和應用產品的各項特性。

TABLE OF CONTENTS
Revision History....................................................................................................................................................... 2
Contents of Tables ................................................................................................................................................... 6
Contents of Figures ................................................................................................................................................. 7
Chapter 1 PIN INFORMATION.............................................................................................................................. 8
1.1 PIN ASSIGNMENTS ................................................................................................................................ 8
1.2 PIN DESCRIPTION.................................................................................................................................. 9
Chapter 2 UNIVERSAL RX(1M to 8M15P) ......................................................................................................... 10
2.1 FUNCTIONAL OVERVIEW .................................................................................................................... 10
2.1 ANALOG FRONT END (CLAMP, ANTI-ALIASING FILTER, EQ FILTER) ...............................................11
2.2 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION)...................................11
2.3 YCS (Y/C SEPARATOR) .........................................................................................................................11
2.4 LUMA PROCESSING..............................................................................................................................11
2.5 CHROMA PROCESSING........................................................................................................................11
2.6 DATA OUTPUT ORDER & DIRECTION CONTROL .............................................................................. 12
2.7 OUTPUT FORMAT................................................................................................................................. 13
2.7.1 ITU-R BT.656/BT.1120 FORMAT ................................................................................................. 13
2.7.2 ITU-R BT.601 FORMAT ............................................................................................................... 13
2.7.3 VIDEO OUTPUT TIMING INFORMATION .................................................................................. 14
2.8 OUTPUT MODE..................................................................................................................................... 16
2.8.1 SINGLE OUTPUT MODE ............................................................................................................ 16
2.8.2 2-MULTIPLEX OUTPUT MODE .................................................................................................. 17
2.9 297MHz INTERFACE AND MULTI STANDARD OUTPUT MODE ......................................................... 18
2.10 Video Frame Control .............................................................................................................................. 18
Chapter 3 COAXIAL PROTOCOL ...................................................................................................................... 19
3.1 PELCO PROTOCOL .............................................................................................................................. 19
3.2 A-CP(AHD-Coaxial protocol).................................................................................................................. 20
Chapter 4 I2C INTERFACE................................................................................................................................. 22
Chapter 5 REGISTER DESCRIPTION................................................................................................................ 23
5.1 REGISTER ADDRESS........................................................................................................................... 23
5.1.1 BANK0 Register(0x00~0x3D) : VIDEO........................................................................................ 23
5.1.2 BANK0 Register(0x40~0x7A) : VIDEO........................................................................................ 24
5.1.3 BANK0 Register(0x80~0xA1) : VIDEO_ENABLE & Delay .......................................................... 25
5.1.4 BANK0 Register(0xA8~0xF4) : STATUS ..................................................................................... 26
5.1.5 BANK1 Register(0x80~0x9F) : IP Power Down........................................................................... 27
5.1.6 BANK1 Register(0xB0~0xBF) : MPP........................................................................................... 27
5.1.7 BANK1 Register(0xC0~0xCF) : OUTPUT PORT......................................................................... 27
5.1.8 BANK3 Register(0x00~0x7F / 0x80~0xFF ) : COAXIAL CH1~2.................................................. 28
5.1.9 BANK3 Register(0x00~0x1F / 0x80~0x9F ) : COAXIAL CH1~2.................................................. 28
5.1.10 BANK3 Register(0x20~0x5F / 0xA0~0xDF ) : COAXIAL CH1~2................................................. 29
5.1.11 BANK3 Register(0x60~0x79 / 0xE0~0xF9 ) : COAXIAL CH1~2.................................................. 30
5.2 Register Description ............................................................................................................................... 31
5.2.1 VIDEO Registers ......................................................................................................................... 31
5.2.2 State Registers ............................................................................................................................ 40
5.2.3 Power Down Registers ................................................................................................................ 42
5.2.4 MPP Control Registers ................................................................................................................ 43
5.2.5 Video Output Control Registers ................................................................................................... 44
5.2.6 COAXIAL Registers ..................................................................................................................... 46
Chapter 6 ELECTRICAL CHARACTERISTICS.................................................................................................. 52
6.1 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 52
6.2 RECOMMENDED OPERATING CONDITION........................................................................................ 52
6.3 DC CHARACTERISTICS ....................................................................................................................... 52
6.4 AC CHARACTERISTICS........................................................................................................................ 53
6.5 RECOMMENDED POWER-ON/OFF, PLL SEQUENCE ........................................................................ 54
Chapter 7 PACKAGE INFORMATION ................................................................................................................ 55

Contents of Tables
Table 1.1 N5 PIN Description........................................................................... 9
Table 2.1 Data Output Pin Order Control ............................................................. 12
Table 2.2 Output Clock and Data Direction Control .............................................. 12
Table 2.3 Each Port 1-Channel Normal mode or X-Format Setting ................................................. 16
Table 2.4 Each Port 2-Channel Normal mode or X-Format Setting ........................................... 17
CONTENTS OF FIGURES
Figure 1.1 N5 Pin Assignments............................................................................. 8
Figure 2.1 Universal RX Video Processing of N5 ........................................................... 10
Figure 2.2 Region of active is constant................................................................... 13
Figure 2.3 BT.601 Interface............................................................................... 13
Figure 2.4 AHD720P@30P/25P, 60P/50P Horizontal Timing Diagram ............................................. 14
Figure 2.5 AHD720P@30P/25P, 60P/50P Vertical Timing Diagram ............................................... 14
Figure 2.6 AHD1080P@30P/25P Horizontal Timing Diagram ..................................................... 15
Figure 2.7 AHD1080P@30P/25P Vertical Timing Diagram.........................................................15
Figure 2.8 Block Diagram of Single-Channel Output .........................................................16
Figure 2.9 Block Diagram of of Multiplexed 2-Channels Output ............................................... 17
Figure 3.1 Coaxitron Active line .......................................................................... 19
Figure 3.2 Description of One Coaxitron Bit .................................................................19
Figure 3.3 Coaxitron Bit Timing ...........................................................................20
Figure 3.4 Data Structure of Coaxitron Origins (VBI 18th)...................................................20
Figure 3.5 A-CP Active line ................................................................................20
Figure 3.6 Description of A-CP One Data Bit.................................................................21
Figure 3.7 Data A-CP Bit Timing............................................................................. 21
Figure 3.8 Data Structure of Coaxitron Origins (VBI 17th)...................................................21
Figure 4.1 I2C Timing Diagram................................................................................ 22
Figure 4.2 I2C Slave Address Configuration....................................................................22
Figure 6.1 SCL and SDA Timing Diagram........................................................................53
Figure 6.2 Recommended Power-on/off Sequence................................................................54
Figure 7.1 N5 54Pin Package Information ....................................................................55

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