MC20901 DATASHEET 手冊英文版

MIPI CSI2 Brdge芯片，轉(zhuǎn)成LVDS信號，便于FPGA接收。MC20901 5 Channel FPGA Bridge IC for MIPI D-PHY Systems and SLVS to LVDS Conversion。
1 General Description
The MC20901 is a high performance 5 Channel FPGA bridge IC, which converts MIPI D-PHY compliant input streams into LVDS high speed and CMOS low speed output data streams.
The MC20901 can also convert an SLVS signal into an LVDS signal. The MC20901 outputs can be directly connected to FPGAs or DSPs.
Data rates range from 0 Mbps to 2.5 Gbps in HS (High Speed) mode and up to 20 Mbps in LPDT (Low Power Data Transmission) mode.
2 Key Features
Input is compliant to MIPI D-PHY interfaces using the DSI, CSI-1 and CSI-2 standards
o HS mode data rate: up to 2.5 Gbps
o LPDT mode data rate: up to 20 Mbps
Conversion of SLVS input to LVDS output
o SLVS data rate: up to 2.5 Gbps
BTA (Bus Turnaround option for Channel A or E)
Pin swap option (all channels simultaneously)
5 Channel device (e.g. 4x DATA, 1x CLK)
D-PHY input termination automatically switched depending on HS or LP mode
No additional level shifters needed
Arbitrary power up sequence
Available as a bare die
o RoHS compliant, Pb-free
Available in a TQLMP-48 package
o 7mm * 7mm * 0.9mm
o 0.5mm pitch
o RoHS compliant, Pb-free


Table of Contents
1 General Description .......................................................................................................................... 4
2 Key Features ..................................................................................................................................... 4
3 Block Diagram ................................................................................................................................... 5
3.1 Block Diagram ........................................................................................................................... 5
4 Parametrics ....................................................................................................................................... 6
4.1 Absolute Maximum Ratings....................................................................................................... 6
4.2 Recommended Operating Conditions ....................................................................................... 6
4.3 DC Characteristics..................................................................................................................... 7
4.4 AC Characteristics ..................................................................................................................... 8
5 Package Information ......................................................................................................................... 9
5.1 TQLMP-48 Package .................................................................................................................. 9
5.2 Pin Description........................................................................................................................... 9
5.3 Package Information................................................................................................................ 11
6 Application Notes ............................................................................................................................ 12
6.1 Application Overview ............................................................................................................... 12
6.2 D-PHY to FPGA Bridge Application......................................................................................... 13
6.3 D-PHY to FPGA Bridge Application with Bus Turnaround ...................................................... 14
6.4 Signal Levels ........................................................................................................................... 15
6.4.1 HS-X-P and HS-X-N LVDS Outputs *) ............................................................................. 15
6.4.2 LP-X-P and LP-X-N CMOS Outputs *)............................................................................. 15
6.4.3 DPHY-X-P and DPHY-X-N Inputs *) ................................................................................ 15
6.4.4 GPIO-0, GPIO-1, BTA, PINSWAP CMOS Inputs............................................................. 15
6.5 Configuration Using GPIO-0 and GPIO-1................................................................................ 15
6.6 Configuration Using BTA ......................................................................................................... 15
6.7 Configuration Using PINSWAP ............................................................................................... 15
6.8 Input to Output Signal Diagram ............................................................................................... 16
7 Legal Disclaimer Notice .................................................................................................................. 17
8 Contact Information......................................................................................................................... 17

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2021-3-25 00:56 上傳

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